MENU

An Efficient and Safe Approach of Radar Signal Capturing and Processing

An Efficient and Safe Approach of Radar Signal Capturing and Processing

Technology News |
By eeNews Europe



Automotive Radar Evolution

Radar has a substantial history in Automotive of more than two decades. In the early days radar was mainly used for applications like adaptive cruise control (ACC), which was an optional comfort feature in luxury cars. Radar systems were widely used in the military and avionics industry due to its capability to directly measure relative position and relative speed of objects in the free space. However, in the high-volume automotive market radar technology was not very attractive because of high cost.

Over the last decade advancements in micro-wave chip sets and digital signal processing devices enabled a significant cost reduction of radar systems. Meanwhile car makers start to offer car models with radar sensors as standard equipment. Besides ACC, radar sensors are used for a manifold of use cases like autonomous emergency brake, blind spot detection and rear or front collision warning. Beyond cost reduction, new radar sensors have to fulfill ever increasing technical requirements, e.g. larger detection range, higher range resolution, wider angle of view and improved object discrimination with multi-target detection capability. On top of these system requirements also other automotive-specific aspects like functional safety, lower power and reduction of form factor have to be taken into account.

In former automotive radar sensors FMCW (frequency modulated continuous wave) technique with slow ramps (aka chirps) has been used, because of restrictions in the RF front-end chip set and limited availability of baseband processing chips for the harsh automotive environment. This technique was rather slow (e.g. 30ms chirp time) and provided limited resolution and limited multi-target capability. Thanks to advancements in the development of semiconductors, modern automotive radar sensors are based on the fast chirp technique. As the name indicates the frequency ramps occur at a higher rate and have a reduced ramp time in the range of 10-100 microseconds.


At this ramp speed objects in the surrounding can be assumed to be quasi-stationary, i.e. relative movement of the objects can be ignored within a ramp period.

Fig. 1: Fast Chirp signals (single Rx channel). For full resolution click here.
Explanation: (a) Tx signal sTx(t) and Rx signal sRx(t), (b) Delta signal sTx(t) – sRx(t); (c) phase of sTx(t) – sRx(t)

In Figure 1(a) an exemplary fast transmit signal sTx(t) and the received echo sRx(t) is depicted. The frequency difference signal of transmit minus receive signal (see Figure 1(b)) is generated by the down mixer unit. The delta frequency is directly proportional to the distance (range) to the objects that cause a reflection of the electro-magnetic wave. With former slow ramps the delta frequency was ambiguous, because it was comprised of the range component and the Doppler shift component, which was caused by the relative speed of the object. To resolve this ambiguity ramps with different directions and slew rates were used. Fast chirps do not have to cope with this ambiguity due to the quasi-stationary situation. However, a single chirp won’t allow the measurement of the relative speed. By analyzing multiple successive chirps the Doppler shift can be retrieved from the phase information (see Figure 1(c)). By doubling or even quadrupling the number of receive channels the azimuth (horizontal) angle of the surrounding objects can be determined, e.g. with a digital beam forming approach.


Radar Capture and Processing Hardware

A high performance analog-to-digital converter (ADC) and a digital signal processing (DSP) device is required for the analysis of the delta frequency. Before the ADC samples the input and converts the down mixed analog baseband signal into the digital domain, the signal has to be filtered with an anti-aliasing filter and boosted with a low noise amplifier. An equalizer that compensates range-dependent signal losses would be also beneficial. The digitized signal is captured and analyzed by the signal processor, which extracts range, velocity and angle information from the data by applying following steps as summarized in Figure 2.

Radar Signal Processing Steps

The radar signal processing steps consist of two orthogonal FFTs, digital beam forming and a target detector. The first FFT determines the range of the objects that cause a reflection of the signal. It is called range FFT (see Figure 2(b)). As mentioned earlier, frequency shift is directly proportional to the propagation delay, respectively the distance to the object. When the range FFTs of all chirps and all receive channels have been calculated, the relative velocity Δv of the objects can be determined by executing the orthogonal Doppler FFT of the range FFT results. This is done by collecting the same range bins of all range FFTs from a single receive channel as input data for the Doppler FFT (see horizontal blue bars in diagrams of Figure 2(b) and 2(c)). Due to the fast chirp approach the same range bins are apart from each other by one chirp period. The relative velocity of objects translates into a phase shift from range bin of chirp (n) to range bin of chirp (n+1), which represents the Doppler frequency. This is repeated for all range bins and all receive channels. The result after range FFT and Doppler FFT is a two-dimensional range-Doppler array per receive channel. The array elements are complex values with a real and imaginary part.

Fig. 2: Radar Signal Processing Steps (4 Rx channels). For full resolution, click here.
(a) Signal Capture; (b) Range FFT; (c) Doppler FFT; (d) Digital Beam Forming, (e) Target Detector; (f) Object Tracker


As the third step the azimuth angle of the objects can be retrieved by applying digital beam forming (DBF) to the range-Doppler arrays across the multiple receive channels. A simple yet efficient way of DBF is the addition of pre-defined phase shift values to the range-Doppler array elements to compensate for the propagation delays n*τ, as depicted in Figure 3.

Fig. 3: Digital Beam Forming. For full resolution click here.

The phase-shift values are dependent on the characteristics and dimensions of the physical antenna patches, the receive channel and the targeted angle. This is also called static DBF and can be simply realized by complex multiplications of the individual range-Doppler array elements with the predefined phase-shift values, followed by the summation across all receive channels. The abovementioned procedure has to be repeated per digital beam. This results in a three dimensional complex range-Doppler-beam/azimuth array as shown in the diagram of Figure 2(d).
Before continuing with the final radar signal processing step, the complex array has to be converted into an array with absolute values, which represent absolute power figures. The array elements are superimposed by clutter from multi-path reflections, background noise and interference from other sources in close proximity. The clutter can greatly vary in spatial and time domain.

Therefore an adaptive filter is required that can cope with the varying conditions while finding the most probable targets. A reliable filter is the OS-CFAR detector (see step (e) in Figure 2). OS-CFAR means “Order Statistic Constant False Alarm Rate”. So as to maintain the constant false alarm rate the threshold in a CFAR detector is set on an element by element basis according to the estimated noise/clutter power, which is determined by processing a group of reference elements surrounding the element under investigation (EUI). The surrounding elements are first sorted by their absolute values. Secondly, the value of the sorted element at rank R is the reference element that is compared with the EUI. When the element under investigation is lower than the reference element the EUI is set to 0. Otherwise EUI becomes a target. By selecting a higher rank R the filter becomes more restrictive in detecting targets. In addition, an offset value can be added to the reference element at rank R to make the detector more robust.


The OS-CFAR detector is applied to each element of the range-Doppler-azimuth power array. The output is a sparse three dimensional target array that is passed on to an application-specific tracking algorithm. This tracker is an estimator that uses the target array as reference input in order to correlate the target information with existing tracks, i.e. objects. Moreover the tracker also takes care of removing old tracks and creating new tracks.

Additional Key Requirements in Automotive Radar

As mentioned in the beginning, besides a superior radar signal processing performance, other aspects like functional safety, low power and smaller sensor size are gaining importance in Automotive. Radar sensors are providing safety-critical commands to chassis systems like anti-lock braking, electrical power steering or active suspension that impact the dynamics of a car. E.g. a false positive autonomous emergency brake command can be fatal and hence is rated as safety critical. A power efficient implementation helps to reduce carbon dioxide emissions, simplifies the thermal design of the sensor and may allow using cheaper housing material. Furthermore a low power design makes it easier to reduce the form factor of the sensor due to relaxed power dissipation constraints.

Example of a Radar Capture and Processing Hardware

Now let’s look at an actual example that is based on the AFE5401-Q1 and the TDA3xR System-on-Chip (SoC) from Texas Instruments as depicted in Figure 4. This exemplary implementation has 4 receive channels. The TDA3xR device family facilitates up to 8 receive channels allowing the implementation of a scalable set of radar sensors.


Fig. 4: System Block Diagram for Radar Baseband Processing (Example). For full resolution click here.

Both devices are or will be Automotive qualified and are optimized for radar applications. The AFE5401-Q1 is a high-performance analog front-end with 4 identical channels supporting simultaneous conversion. Each channel comprises a low-noise amplifier (LNA), an optional equalizer, a programmable gain amplifier (PGA) and an anti-aliasing filter followed by a high-speed 12-bit analog-to-digital converter (ADC) at up to 25 MSPS per channel. The exhaustive pre-conditioning considerably reduces the need for additional external components. The equalizer can compensate range dependent losses.


A sampling rate of 25 MHz supports faster chirps with enhanced range and velocity resolution. A 12-bit parallel digital output with a clock signal and two programmable sync signals enables a seamless connection with one of the video input ports of the SoC. Parity information can be optionally presented at a 13th data line, which facilitates end-to-end protection from the internal ADC output to the memory of the TDA3x. The digital data of the four channels is streamed out in an interleaved manner, i.e. every fourth sample belongs to the same channel. A built-in pattern generator can produce pre-defined test pattern like ramp, toggle pattern or a custom pattern. This feature can be used to verify during start-up or occasionally during normal operation the physical link between ADC and SoC.

The above mentioned programmable ADC features can be configured by the SoC via a serial peripheral interface (SPI). The ADC-frontend is available in a compact 9mm by 9mm QFN package.

As the name indicates the TDA3x is a 3rd generation SoC family developed for Driver Assistance applications. The family is designed from ground up with functional safety and ISO 26262 in mind and is available in different configurations and speed grades. The TDA3xR members of TDA3x family are most suited for Radar applications, as the ‘R’ indicates. The designator ‘x’ is a placeholder for various speed grades allowing a scalable implementation of radar sensors. The TDA3x family comprises a heterogeneous combination of processing elements optimized for the different software tasks. A dual Cortex-M4 sub-system, an Embedded Vision/Vector Engine (EVE) sub-system and up to two C66x floating point DSP sub-systems allow a power efficient implementation of the radar signal processing steps. EVE is a RISC controller with a vector coprocessor that is optimized for high throughput, high processing performance at a low power footprint. It can conduct in real time all range and Doppler FFTs as well as perform digital beam forming for multiple beams. In addition, EVE can re-sort the channel-interleaved ADC data and perform the parity check on the fly at a very low additional load.


The detection of targets and the tracking of objects can be handled by the C66x DSP sub-system. The Cortex-M4s are well suited for configuring the RF components and the AFE5401-Q1, and can administrate and monitor the processing of the other cores. It can also communicate the object information externally. Moreover the TDA3x is equipped with a rich set of peripherals, e.g. video input ports to receive parallel or CSI-2 data from radar front-end, CAN Controllers, various serial interfaces and a QSPI supporting fast quad-lane boot.

The DDR interface can handle various SDRAM types and has an ECC extension for error detection and correction. Internal memories of the TDA3x are also protected with ECC or parity. Besides hardware BIST (built-in self-test for diagnosis of vital parts of the chip) other nifty safety means have been leveraged from Hercules™ TMS570 safety MCU family. This makes TDA3x well suited for safety-critical driver assistance applications like radar. The TDA3xR is available in two package variants, 15mm x 15mm and 12mm x 12mm, whereas the latter is a so-called POP (package-on-package) variant. With the DDR memory on-top of TDA3x the sensor size can be minimized.

Summary and Outlook

The TDA3xR in combination with one or two AFE5401-Q1 devices enables a scalable implementation of short-range, mid-range and long-range radar sensors with 4 to 8 receive channels while software compatibility is maintained. Moreover, the safety features available in TDA3x and AFE5401-Q1 provide a solid foundation for realization of safety critical applications. Both devices are optimized in terms of low power consumption and are available in small packages allowing to shrink the sensor housing. With the POP variant of the TDA3x PCB layout can be simplified and the number of signal layers may be reduced. The performance headroom of the heterogeneous TDA3x architecture permits for example the integration of the AUTOSAR software stack on one of the Cortex-M4s or implementation of sensor fusion for AEB (autonomous emergency brake) in addition to radar signal processing. TDA3xR and AFE5401-Q1 facilitate radar sensor developers to take the next evolutionary step on the way to supersede the driver’s visual sense needed for autonomous driving.

References
TDA3x (https://www.ti.com/product/tda3)
AFE5401-Q1 (https://www.ti.com/product/afe5401-q1)

About the author:

Peter Aberl studied electronic engineering with focus on data processing at the Munich University of Applied Sciences. He started to work as Applications Engineer in the area of Automotive Electronics at Texas Instruments (TI) in 1994. Since 2009 he supports TI’s Driver Assistance System-on-Chip and Hercules Safety MCU products at European Automotive customers. He is Senior Member Technical Staff (SMTS) and Principal Field Application Engineer.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

Linked Articles
10s