Figure9: A Typical SOC
In most of the cases, all these analog IP's have separate isolated power supplies at chip level due to reasons like noise and different operating voltage level. Digital part in SoCs is also divided in multiple power domains to save the overall power in low-power modes. The signals from outside world interact directly with the analog IP interfaces. The designer has to keep an account of the ESD protection available for each external interface, i.e., I/O pins and power pins. Due to different power supplies and analog to digital interface communication or vice versa, there are several signals crossing from one power domain to another as a result the analog IP’s required to have an in build ESD protection.
Before going in detail for ESD protection mechanism, few combinations for ESD on SoC need to understand as mentioned below:
- The signal from external I/O goes directly to an analog IP working on isolated supply.
- The signal from analog IP which works at isolated supply goes to digital interface in SoC or vice versa.
- The signal from external I/O goes to digital logic in SoC.
Best practices for analog IP signal connections to external I/O and digital interfaces:
Below are the different points that need to be taken care for ESD protection while connecting to an analog IP pin to external I/O or digital interface.
- Add small diodes called spot diodes in analog IP when the gate of a device in analog IP is connected to external I/O interface. These diodes will be connected from the signal to power/ground supply at which the receiving analog IP is working.
- When a signal from external I/O is connected to gate of analog IP, use the resistive path from the external I/O “pad” pin for connection. It is always recommended to add small diodes after the resistor from the signal on I/O pad to the I/O pad power and ground