Cypress Semiconductor's recent update to its HyperRAM memory DRAM device is addressing the automotive industry's preference for fewer moving pieces with a lower pin count. The company is now sampling its new high-speed, self-refresh DRAM based on its low-pin-count HyperBus interface.
The 64Mb HyperRAM is designed to serve as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications, said Rainer Hoehler, VP of the flash business unit at Cypress, in an interview with EE Times. Microcontrollers often do not have enough integrated memory for high-resolution graphics or data-intensive firmware algorithms.
Hoehler said the new HyperRAM is best used when paired with Cypress HyperFlash NOR flash memory in an embedded system—both the flash and RAM reside on the same 12-pin HyperBus. The combination reduces the pin count by at least 28 pins, he said, compared to traditional systems using SDRAM and Dual-Quad SPI solutions that require upwards of 41 pins on two buses for data transactions, which simplifies designs and lowers PCB cost. The new Cypress HyperRAM devices operate with a read/write bandwidth of up to 333 MBps and are available in 3V and 1.8V supply voltage ranges.
The embedded systems-focused Cypress is seeing more demand for higher performance for interfaces, said Hoehler, but with lower pin counts, both in automotive applications and IoT, particularly industrial IoT, where more process power is required from a microcontroller. “They are running out of on-chip RAM, but they want to keep a small pin count and a small PCB with high read and write bandwidth.
He said designers are looking to reduce overall system cost by combining DRAM and flash in a single package if possible. Cypress' HyperRAM and HyperFlash are addressing a gap between systems that need high performance DRAM with