The first Aurix architecture based microcontroller (MCU), part number TC275T, contains three TriCore processor cores (version 1.6). Two of these are optimized for maximum performance (high-performance TriCore CPU 1.6P) and can execute up to three instructions in one cycle at a maximum clock frequency of 200 MHz. With the third core, a high-efficiency TriCore CPU 1.6P, lowest possible power consumption and an efficient data exchange with the peripherals are the most important factors. It can execute a maximum of one instruction per cycle and is currently clocked at a maximum of 200 MHz.
The UDE 3.3 allows management and control of the various TriCore-CPUs within one user interface. This is supported by a flexible multicore program loader that enables the loading of program code and data as well as symbol information separately for each core. Management of the cores is carried out by a multicore run control manager, which offers a definition of core groups. Therefore, a very flexible control of the run-time behavior of the complex architecture is possible.
If required, programs for the integrated hardware security module (HSM) can also be developed with the UDE version 3.3. The HSM offers vehicle manufacturers a configurable system integrity protection of their control units and, due to its flexibility, is also equipped to meet future security requirements. In addition, the UDE 3.3 supports programming speed of the enlarged flash memory of 4 MByte by up to 20 times faster than in the previous AUDO family.
The UDE 3.3 also makes debugging of program code on the new high-performance Generic Timer Module (GTM) easier. With the help of an own instruction set, various tasks in the areas of time measurement, collection and comparison of digital input signals as well as complex algorithms such as pulse width modulation (PWM) can be solved with the GTM.
The On-Chip Debug System (OCDS), which is well-known from the previous TriCore architecture for the AUDO family, was optimized further for