Error simulator facilitates large HiL tests

June 14, 2012 // By Christoph Hammerschmidt
Automotive design and test tools vendor dSpace has announced a new release of its Scalexio error simulation system. The current iteration offers easier partitioning of large models. Also the number of I/O channels has been increased.

Scalexio facilitates scaling hardware-in-the-loop (HIL) simulation for large, computationally demanding simulation models and large quantities of input and output (I/O) channels. Extensive models with numerous I/O channels can now be distributed conveniently across several processor cores to guarantee real-time simulation. Scalexio also provides adaptble failure simulation technology that scales with growing numbers of I/O channels.

Scalexio utilizes several processor cores to compute complex simulation models. There are two ways to distribute a model on the processor cores: One is to create the overall simulation model first and then partition it. The other is to design it as several submodels from the beginning. The main advantage of using submodels is that they can be developed and maintained simultaneously, and independently by several teams, reducing the overall model development and validation effort. Additionally, the compile and load times are dramatically reduced whenever individual parts of the model are modified.

The dSPACE ConfigurationDesk software assigns the submodels to the processor cores in the Scalexio system, configures intermodel communication and connects the submodels when necessary. Because ConfigurationDesk keeps model development and configuration separate, the configuration settings are preserved even when modifications are made to some model parts or to the
entire system model.

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