The I6500 has been architected to provide a highly scalable solution which can coherently implement optimized configurations of CPU cores within a cluster (‘Heterogeneous Inside’) as well as a variety of configurations of CPU clusters and GPU or accelerator clusters on a chip depending on the requirements of the system (‘Heterogeneous Outside’).
In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels. Then, the latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system efficiency.
Based on a superscalar dual issue design implemented across generations of MIPS CPUs, Simultaneous Multi-threading (SMT) enables the execution of multiple instructions from multiple threads every clock cycle, providing higher utilization and CPU efficiency.
Real time hardware virtualization (VZ) allows designers to save costs by safely and securely consolidating multiple CPU cores with a single core, saving power where multiple cores are required, and dynamically and deterministically allocating CPU bandwidth per application. The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, makes the I6500 suitable for applications which require deterministic code execution.