NXP adds performance, meets SIL3 criteria, with I.MX 8 MCUs

March 17, 2017 // By Graham Prophet
NXP presents its i.MX 8X microcontroller family as delivering increased safety, reliability and scalability to industrial applications. It is the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3).

This series of MCUs, NXP, broadly follows on from the top of the I.MX 6 range, and provides users with a path to a 64-bit architecture. NXP builds the parts in a fully-depleted silicon-on-insulator (FDSOI) process developed with Samsung, which NXP says yields large gains in power-performance metrics. These devices will run at up to 1.2 GHz and feature graphics processing units (GPUs) to handle advanced display tasks.


NXP says it is extending the scalable range of the i.MX 8 series of applications processors with the introduction of this i.MX 8X family, which uses common subsystems and architecture from the higher-end i.MX 8 family with pin-compatible options and the highest level of software reuse. Power efficiency, cooler operation and longer battery life are enhanced by optimizing ARM Cortex-A35 and Cortex-M4F CPUs in FD-SOI technology. Automotive safety certification is supported up to ASIL-B for cameras and displays by employing an advanced SafeAssure display controller with failover safety planes and a real time domain that is independent of the Cortex-A CPUs and 3D graphics accelerators. Industrial safety certification is supported up to SIL 3 by using ECC on the L2 cache and DDR3L memory interfaces, enabled by several commercial RTOS solutions from QNX, Green Hills and others.


Built with a high level of integration to support graphics, video, image processing, audio and voice, the i.MX 8X family of processors is suited for industrial automation, HMI, industrial control, robotics, building control, automotive cluster, display audio infotainment, and telematics applications. It integrates up to four 64-bit ARMv8-A Cortex-A35 cores, a Cortex-M4F core, a Tensilica HiFi 4 DSP, Vivante hardware accelerated graphics and video engines, advanced image processing, advanced SafeAssure display controller, LPDDR4 and DDR3L memory support and a set of input-output controllers. Capable of driving up to three simultaneous displays – two 1080p screens and one parallel WVGA display – the new devices include:

- i.MX 8QuadXPlus with four Cortex-A35 cores, a