Spansion interface speeds up NOR Flash throughput

February 18, 2014 // By Christoph Hammerschmidt
Instrument clusters, infotainment system, and advanced driver assistance systems today are typically equipped with a sophisticated graphical user interface that requires strong graphic performance. Flash memory provider Spansion, Inc. has developed a data bus interface that could significantly the throughput in these embedded systems. Other potential applications include digital cameras, factory automation, handheld displays and the like.

The HyperBus interface is introduced along with a family of NOR memory devices implemented in Spansion's HyperFlash technology. Thanks to the Hyperbus, these devices provide a read throughput of 333 megabytes per second. This is more than five times higher than the fastest competitor technology, Quad SPI flash. At the same time, Spansion reduced the number of I/O pins to one third, compared to parallel NOR memory. The HyperBus interface consist of an 8-pin address/data bus, a 2-signal differential clock, as well as the usual 'chip select' and 'read data strobe' pins. The low pin count helps reducing the overall system costs, Spansion argues.

The high read throughput will enable much faster boot times. It also allows program execution directly from the NOW flash, reducing the effort for code shadowing and thus the amount of RAM, Spansion explained.

For the start, the company plans to offer three densities - 128 Mbit, 256 Mbit and 512 Mbit. The latter one will be sampling in Q2/2014.

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