Suitable to the HyperBus interface, the new memory product family will be named HyperRAM. Offering a data rate of up to 333 MByte per second, the memory components will enable to significantly increase the performance of embedded applications. Additional benefits for chipset providers result in lower controller pin count with less complex PCB designs, smaller packages, and lower costs at higher performance in cases where HyperRAM can replace conventional DRAM chips. While developed by Spansion, the HyperBus interface is implemented by a variety of SoC and microcontroller manufacturers.
According to the agreement between Spansion and ISSI, both companies will have the right to sell HyperRAM products. The first such products will become available in the first half of 2015.
The 12-pin HyperBus interface contains an 8-pin address/data bus, a differential clock signal on 2 pins, one Chip Select and a Read Data Strobe Controller. It is intended to enable a wide range of high-performance applications such as automotive instrument clusters, infotainment and navigation systems, advanced driver assistance systems, handheld displays, digital cameras, factory automation equipment and medical diagnostic devices - plus a variety of consumer and home automation appliances.