Fraunhofer IIS has developed a hybrid prototype of an ASIC (application specific integrated circuit) and an FPGA (field-programmable gate array) to implement all these features of the new physical layer. The analog frontends (DAC and ADC) were implemented in the ASIC. This allows evaluation of the real circuit performance with all parasitic effects and getting reliable estimates for the overall power consumption, once analog and digital functionality is integrated together on a single chip. Moreover, with this implementation, the highest risk in system development was already addressed and the feasibility of the complete system could be shown.
The digital signal processing chain has been implemented in the FPGA. This gives flexibility in implementation details and parameterization of the different signal processing blocks. The implementation can also be tailored to the specific circuit performance of the analog frontends. After testing, debugging and optimization of features like self-adaptation, frequency synchronization and the link-start-up-procedure, the final tested version of the digital part can then be migrated to the ASIC. During the development, the performance of virtually all implementations of the converters and signal processing blocks was pushed, and match the state-of-the-art in their respective fields.