10 Gbps Physical Layer for Single Twisted Pair: Page 3 of 5

September 10, 2015 //By Norbert Weber, Conrad Zerna, Fraunhofer IIS
10 Gbps Physical Layer for Single Twisted Pair
Applications like advanced driver assistance systems (ADAS) and passenger infotainment drive data rates in automotive vehicles. To realize the lightweight and fuel efficient cars of the future, it is mandatory to increase the data rate, to get more bits over the same channel in the same time. This article introduces an elegant method to increase the data bandwidth in a single twisted pair (STP) cabling.
More specifically, a PAM4 modulation format was chosen. To facilitate the signal processing in the digital domain, a high-speed Digital-Analog-Converter (DAC) and an Analog-Digital-Converter (ADC) were implemented. The cable transfer function (low pass characteristic) is now compensated by two digital filters at transmitter and receiver working in tandem. These filters are adapted at run-time. The bit error rate is achieved and secured by adding error correcting redundancy encoding and decoding to the transmission system (so-called forward error correction).

CMOS implementation

Fraunhofer IIS has developed a hybrid prototype of an ASIC (application specific integrated circuit) and an FPGA (field-programmable gate array) to implement all these features of the new physical layer. The analog frontends (DAC and ADC) were implemented in the ASIC. This allows evaluation of the real circuit performance with all parasitic effects and getting reliable estimates for the overall power consumption, once analog and digital functionality is integrated together on a single chip. Moreover, with this implementation, the highest risk in system development was already addressed and the feasibility of the complete system could be shown.

The digital signal processing chain has been implemented in the FPGA. This gives flexibility in implementation details and parameterization of the different signal processing blocks. The implementation can also be tailored to the specific circuit performance of the analog frontends. After testing, debugging and optimization of features like self-adaptation, frequency synchronization and the link-start-up-procedure, the final tested version of the digital part can then be migrated to the ASIC. During the development, the performance of virtually all implementations of the converters and signal processing blocks was pushed, and match the state-of-the-art in their respective fields.

Fig. 1: Prototyping platform: a flexible FPGA board by prodesign, which can accommodate custom extension boards © Prodesign

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