10 Gbps Physical Layer for Single Twisted Pair: Page 4 of 5

September 10, 2015 //By Norbert Weber, Conrad Zerna, Fraunhofer IIS
10 Gbps Physical Layer for Single Twisted Pair
Applications like advanced driver assistance systems (ADAS) and passenger infotainment drive data rates in automotive vehicles. To realize the lightweight and fuel efficient cars of the future, it is mandatory to increase the data rate, to get more bits over the same channel in the same time. This article introduces an elegant method to increase the data bandwidth in a single twisted pair (STP) cabling.

A picture of the prototyping platform can be seen in figure 1. It shows a flexible FPGA board (by the company “prodesign”), which can accommodate custom extension boards, one of which is hosting the ASIC with the analog frontends. From the performance of the analog chip and the complexity of the digital circuitry in combination with the required clock frequency, the overall power consumption of the targeted integrated system can be estimated. As a result, a transmitter and receiver pair will consume less than 1 Watt power on a 65 nm CMOS process. The latency of raw data through the link is below 10 µs even in the FPGA-based implementation. A picture of the implemented ASIC can be seen in figure 2. Data transmission experiments have begun recently. Although the engineering team is currently at about 80% of targeted throughput, testing and parameterization is ongoing and they are confident about pushing the envelope on this figure in the near future.

Fig. 2: The analog frontends (DAC and ADC) were implemented in the ASIC
© Fraunhofer IIS

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