Achieving high currents on PCBs with fine-pitch SMD components: Page 2 of 3

March 28, 2011 //By Peter Mauer
Achieving high currents on PCBs with fine-pitch SMD components
Peter Mauer, the head of electronics design for Semikron Elektronik explains how to achieve high currents on PCBs with fine-pitch SMD components.
see figure 2.


Fig. 2: PCB layout with 70 and 105µm thick copper.

Unfortunately, it is not possible to achieve fine pitches (clearances) on the 70µm-thick outer layers at a reasonable cost. Here, the ratio of circuit board conductor width to height would result in behaviour in production that is difficult to predict. An additional 35µm layer pair would resolve this problem technically; unfortunately, however, this would negatively impact the production costs.

Alternatively, in place of SMD components, traditional components with no fine-pitch clearances could be used and 70µm-thick copper used for the outer layers. This would normally result in a larger PCB. Another problem here is that some components are only available in fine-pitch technology, meaning that circuit redesign would be necessary.

Wirelaid technology as a compromise
A new technology available from a number of manufacturers such as Jumatech, Häusermann or others is wirelaid technology. Here, a wire with a rounded or rectangular cross-sectional area is integrated into the stackup design directly beneath the outer layer. In our circuit shown on figure 3, ribbon wiring with a 0.5mm-high and 4mm-wide cross-section is used.



Fig. 3: Wirelaid technology whereby a wire with a rounded or rectangular cross-sectional area is integrated into the stackup design directly beneath the outer layer.


In a micro-welding process, the copper wire is welded (or bonded) on the outer layer to form a positive-locking connection. The given outer FR4 dielectric layer is slightly thicker than usual and contains more resin, meaning that the wire is pressed into the FR4 layer. Using Allegro or OrCAD PCB Editor, a layer for the copper wire was defined directly below the top layer that describes the wire routing – see figure 4.



Fig. 4: A 35µm layout in wirelaid technology, shown in Allegro PCB Editor.


In the first internal signal layer, a Route Keep Out was defined below the wire. During the pressing process, the wire cannot form a short

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