The HyperFlash memory pinout overlays nicely onto the dual QSPI pinout, which makes the migration path for designers from existing QSPI designs to a faster performance as easy as possible and offers a fast back-up solution. It also allows system applications to be scaled to different levels of flash performance when paired with compatible controllers, giving OEMs the ability to offer different product models with a single design. HyperBus implements a low pincount bus interface with a simple read/write protocol which is suitable for both memories and peripheral interfaces. Especially for instrument cluster applications and displays with high resolution, instant-on GUI requirements, this technology enables the balance between system performance, cost and space efficiency. In combination, the Spansion HyperFlash Memory can be a solution to some of the bandwidth issues that have confronted NOR users in the past.
The universal footprint of HyperFlash eases the migration from existing QSPI designs to a faster performance and allows system applications to be scaled to different levels of flash performance when paired with compatible controllers, so different product models can be offered with a single design.
Comparing pin count and read throughput
Two of the most significant criteria used to evaluate NOR Flash devices are the sustained read throughput and the number of pins required to implement the bus interface. Comparing different NOR Flash devices and their respective active signal counts we find, that all legacy parallel interfaces require between 30 to 40 pins (see figure 1). The SPI interface has evolved to use a 6 pin QSPI variant that has gained favour when enhanced read throughput is required. The HyperBus interface uses only 12 pins and marks a siginficant improvement delivering higher data throughput than QSPI while using only 6