Answering the call for high performance, high data throughput in automotive applications : Page 3 of 4

September 17, 2014 //By Hiro Ino, Spansion
Answering the call for high performance, high data throughput in automotive applications
Performance and speed are paramount addressing the instant-on and interactive graphical user interface (GUI) requirements of automotive applications like instrument clusters, infotainment and Advanced Driver Assistance Systems (ADAS). Embedded designers must be given the tools to create these high-speed solutions
pins more.

Comparing the pincount of the different Flash memory types.

The HyperBus Interface delivers a substantial improvement in read throughput compared with legacy NOR flash interfaces (see figure 2). With an 80 MB/s read throughput, QSPI has reached performance levels comparable with the asynchronous and page mode interfaces. Parallel NOR burst mode offerings come in around 133 MB/s with environments that expect a mix of wrapped and continuous read transactions. The HyperFlash memories leveraging the Spansion HyperBus Interface provide a new standard for performance by delivering 333 MB/s using a 12-pin interface. The 333 MB/s is achieved with the 1.8 V version of the interface; the 3 V version runs at 100 MHz and provides 200 MB/s.

Compared to legacy NOR flash interfaces, the HyperBus Interface offers a significant increase in read throughput.

Spansion’s current NOR flash family of HyperFlash memories includes 128-Mb, 256-Mb and 512-Mb products. These initial offerings are compatible with either 1.8-V or 3.0-V operating voltages. Engineering samples of the 512-Mb device are available today with fully qualified parts available in the third quarter of 2014. The 128-Mb and 256-Mb HyperFlash densities will follow in early 2015. Spansion will develop higher or lower densities depending upon market demand.


The HyperBus Interface was developed to satisfy the need for higher performance while remaining sensitive to the pin-count constraints of modern microcontrollers. The philosophy behind it was to create a simple burst mode, read/write interface and transaction protocol that can be used by both memories and peripherals. The IOs are derived from LPDDR1 for the 1.8-V HyperBus Interface and from legacy NOR for the 3.0-V HyperBus Interface. Nothing exotic has been deployed, just an optimal usage of existing, market-tested signaling technology.

The Spansion HyperBus Interface has the ability to satisfy the memory requirements for both volatile and non-volatile memories in a large swath of high-performance applications. Although Spansion’s focus is to place memory on the HyperBus Interface,

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