This concept, which ARM calls “Big.LITTLE”, makes it possible to turn off the large A15 cores completely, reducing leakage current levels to zero. Renesas has refined this technique further in the R-Car and enables up to 12 voltage domains to be controlled separately (see Fig. 1). In addition, the maximum clock speed of each of these voltage domains can adapt dynamically to the application’s requirements. If system activity is low, it would be possible to run just one A7 core at a further reduced clock speed and turn off the seven other processors, including the caches. This ticks all the boxes – providing plenty of power while minimising power consumption and leakage.
Fig. 1 Software-controllable power domains
Despite the CPU core’s high computing power, there are still some tasks that need even more. Yet a further increase in clock speed would mean sacrificing low power consumption. The solution is to use dedicated hardware accelerators within the application processor. They have been developed to handle specific tasks and can get by with a fraction of the power supply. Renesas has implemented several of these accelerators in the R-Car. DSP cores handle audio processing, while accelerator IPs support video processing. Every R-Car includes one or more video decoders, which are used to relieve the CPU of HD video decoding tasks. When a user plays a video, seven of the eight CPU cores can be turned off. Image recognition for high-definition camera images is too demanding for a single CPU. This is why the R-Car includes a special image recognition processor – it combines the real-time functions required with low power consumption (See Fig. 2).
Fig. 2 R-Car H2 hardware accelerators
Of all the hardware accelerators, the 3D graphics processor is the largest in every respect. These are often larger than many CPU cores nowadays, and