All these hardware accelerators share their memory with the processors. That enables powerful data transmission between the various components while remaining cost-effective. This is known as Unified Memory Architecture (UMA), but its disadvantage is that the available memory bandwidth can turn into a bottleneck. An increase in the performance of the application processors goes hand in hand with an increase in memory bandwidth, which has to work within tight constraints. Although other applications could get round this issue by simply using wider memory buses, that solution is not practical here. Developers would have trouble using memory buses wider than 64 bits due to the broad temperature requirements and the high level of cost pressure in the automotive market. Increasing the clock speed also has its limits, as times for a single bit are less than 600ps while the signal delay is twice or three times longer on the circuit board. This situation is improved by the use of a multi-step cache concept that avoids unnecessary memory access from the outset.
The R-Car family includes