Processing horsepower for the convergence of data streams: Page 5 of 6

July 03, 2014 //By Christoph Hammerschmidt
Processing horsepower for the convergence of data streams
Renesas Electronics’ second-generation R-Car range is the company’s response to the growing demand for automotive-enabled system-on-chip (SoC) processors for driver infotainment and assistance systems. With more than 25,000 Dhrystone MIPS CPU power and a 3D performance of 260 million triangles, the 8-core R-Car H2 is the flagship of this family based on the latest 28nm silicon process. This article presents the R-Car family’s scalability in a range of automotive applications and highlights the integrated hardware accelerators that enable developers to achieve compelling performance for their applications while keeping power consumption low.
run at similar clock speeds. They can easily use 30 per cent or more of the overall power consumption. Each new generation has about four times more 3D performance than the preceding one because of the growing use of high-definition screens. Choosing the right accelerator for the processor’s performance category makes a significant contribution to reducing power consumption. For the new generation of the R-Car family, Renesas is again using IPs from Imagination Technology. The smallest product in the range, the R-Car E2, provides about the same performance as the R-Car M1 – the previous mid-range product – while the R-Car H2 delivers 8 times more performance, which is four times more than the previous generation while maintaining full software compatibility. A key benefit here is that this increase in power does not come at the cost of power consumption, which has hardly increased at all.

All these hardware accelerators share their memory with the processors. That enables powerful data transmission between the various components while remaining cost-effective. This is known as Unified Memory Architecture (UMA), but its disadvantage is that the available memory bandwidth can turn into a bottleneck. An increase in the performance of the application processors goes hand in hand with an increase in memory bandwidth, which has to work within tight constraints. Although other applications could get round this issue by simply using wider memory buses, that solution is not practical here. Developers would have trouble using memory buses wider than 64 bits due to the broad temperature requirements and the high level of cost pressure in the automotive market. Increasing the clock speed also has its limits, as times for a single bit are less than 600ps while the signal delay is twice or three times longer on the circuit board. This situation is improved by the use of a multi-step cache concept that avoids unnecessary memory access from the outset.

The R-Car family includes

Design category: 

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