an integrated, scalable cache solution. Each CPU has the usual combination of data and command caches, and the A15 and A7 cores each have their own L2 cache. This means that most data and command access can be kept out of the external memory. Without this type of caching, the eight cores would generate 60GB/s memory transfers, while with it this value can be reduced to a much more reasonable 3GB/s. The R-Car H2 uses an additional system cache that is available to all hardware accelerators, including the image recognition processor and the audio DSPs. The 3D graphics accelerator uses tile-based rendering, which uses on-chip memory to render graphics and minimises access to external memory. The external DDR3 SDRAM memory interfaces can be scaled from 16-bit to 64-bit providing memory bandwidth between 2.7 GB/s and 12.8 GB/s, depending on the performance required and the available power dissipation budget (See Fig. 3).
Fig 3: Cache architecture
With all these measures, Renesas has succeeded in developing a scalable application processor family (see Fig. 4) that enables customers to benefit from the performance of the fastest mobile processors available – devices designed to mitigate the challenges in the automotive field. It is now possible to achieve power consumption of under 5W for typical navigation applications. With the integration of image recognition processors and several video interfaces, the R-Car is well equipped for the upcoming driver assistance systems. The R-Car compatible product range allows developers to choose the appropriate product for their application and simply upgrade if the application requires it.
Fig. 4 R-Car generation 2 - A scalable family
About the author:
Peter Fiedler is Manager for Automotive Information Systems in the MCU Marketing & Engineering division of the Automotive Business Group, Renesas Electronics Europe.