Advanced Flash memory for the future of the car: Page 3 of 6

December 19, 2019 //By Author: Yasuhiko Taito, Renesas
Advanced Flash memory for the future of the car
The new 28-nm Flash memory technology achieves larger capacities, faster read operation, and high-level OTA support in automotive microcontrollers

24 MB Embedded Flash Memory – the Industry’s Largest in an MCU, Combined with High-Performance HKMG CMOS Logic Circuits

Renesas has used split-gate MONOS (SG-MONOS) technology combining excellent performance and reliability for embedded flash memory from the 150nm generation onward. Figure 2(a) illustrates the structure of a memory cell. In SG-MONOS flash memory, the stored electric charges are dispersed on the trap sites in the thin silicon nitride (SiN) film, which provides the two advantages. First, defects in the insulator film have minimal impact on the retention of the stored charges, so it is possible to make the cells smaller without degrading reliability. Second, it is easier to make the height of the memory cells match with that of the logic transistors, which will allow flash memory cells to be added without changing the structure and performance of the logic transistors. This advantage becomes particularly significant in cases where the height of the logic transistors decreases at the more advanced process nodes.

Making full use of the above advantages, Renesas has developed the industry’s first automotive flash MCU with HKMG high-performance transistors in corporation with TSMC. On the prototype chip, the memory cells have been shrunk to a size of less than 0.045 μm2, suppressing growth in the overall chip size while achieving 24 MB capacity of embedded flash memory for code storage (code flash: CF), the largest capacity in the industry. The chip also includes 1 MB of flash memory for data storage (data flash: DF) with a rated reprogramming cycle limit of 250,000 cycles.


Figure 2  (a) Structure of SG-MONOS Flash Memory Cell, (b) Affinity with HKMG High-Speed CMOS Logic (Source: Renesas Electronics Corp.)

 

240 MHz Random Access Read Speed – the Industry’s Fastest for Embedded Flash Memory

Word-line (WL) division, as shown in Figure 3(a), is an effective technique to speed up random access reads in flash memory. However, WL division increases the number of WL drivers and repeaters, which increases the area of the gate insulator film of the logic transistors to which the word line voltage (Vwl) are applied. This reduces reliability due to time-dependent dielectric breakdown (TDDB). As shown in Figure 3(b), Renesas resolved this issue by changing the circuit structure of the WL drivers and repeaters, and providing a logic transistor power supply (Vdd), lower voltage than Vwl, as the drive voltage of the NMOS logic transistors at the final driver stage, which has the large gate insulator area.

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