This made it possible to assure sufficient reliability by reducing the total area of the logic transistors to which Vwl is applied. Increasing the total channel width of the WL drivers and repeaters boosts the leak current and lowers Vwl at the end of the supply paths due to resistance along the Vwl lines, and this can degrade random-access performance. To resolve this, Renesas used a distributed Vwl drivers to minimize the effects of wiring resistance. The above circuit techniques ensure reliability while realizing 240 MHz high-speed random-access read performance on the prototype chip – the industry’s highest read performance – over a wide temperature range (junction temperatures from −40°C to 170°C), as shown in Figure 3(c).
New Low-Noise Technology for Programming During OTA Updates
The charge pump circuit, which supplies the programming voltage, operates when the flash memory is programmed, generally resulting in large peak current consumption from the external power supply. If flash programming of an OTA update takes place in a high power-load environment, for example when the car is running and other circuits on the chip are operating, this peak current consumption could generate significant power supply noise, which would necessitate the addition of a large stabilizing capacitor. On the newly developed prototype chip, program operation is divided into two steps as shown in Figure 4(a). The first step employs a low-noise mode in which the programming current (Iprg) flowing to the individual memory cells is reduced to half of the conventional programming current. Even when the programming current is halved, Vths of most memory cells (more than 99 percent) reach the desired level within the same programming time as with the conventional programming current. Then, the programming current – which is the same as the conventional program current – is applied only to the small remaining number of cells (less than 1 percent) that have not yet reached the desired level. Thus, the overall programming current is reduced significantly. As shown in Figure 4(b), the new technology reduces the peak current consumption from the external power supply (Vcc) by 55 percent without reducing write throughput compared to the conventional programming condition.