Renesas has also applied the concept of varying the programming current in the implementation of a high-speed programming mode on the prototype chip. This will reduce flash programming time required in factory programming on customers’ production lines and testing. In the first step of the programming operation, the programming current flowing through each of the memory cells is half that of the conventional approach and the number of cells to which programming voltage pulses are simultaneously applied is doubled, resulting in high-speed programming at 3.3 MB/s. When two macros are used in parallel, high-speed programming at 6.5 MB/s is possible.
Robust and High-Speed Software Switching Following OTA Updates
Renesas has developed an embedded flash memory system suitable for OTA updates that is poised for rapid mainstream adoption in the near future. Figure 5(a) shows an overview of the CPU cluster block and flash memory system block of the prototype chip. To reduce downtime, the CF where the control software is stored is divided into two areas — a storage area for old software and a storage area for new software — and new software is saved in the background when the car is running. The prototype chip has three CPU clusters. Each CPU cluster (designated as CPU cluster n, where n = 0, 1, and 2) is connected via a cross-bar switch to CFn-A and CFn-B, each of which comprises a 4 MB CF macro. Making full use of the total 24 MB flash memory capacity, a control software storage area totaling 12 MB and a storage area for new software of equivalent size are provided for the three CPU clusters.