To prevent malfunction after a software update or switching interrupt, multiplexing is provided for the software and setting information (OPBT), and history data and status flags (SWT0, SWT1, FLG, etc.) have been added. This ensures robust operation that allows executable control software to be selected reliably. Figure 5(b) shows OTA operation when updating the control software of multiple MCUs installed in a single vehicle. Downtime can be reduced by first storing the new software in the individual MCUs while the car is running and then switching the flag information in all the MCUs when the ignition is turned off. The flag information update time is dominated by erase time. Fast erase of SG-MONOS cells by band-to-band tunneling (BTBT) contributes to fast FLAG update time of less than 1ms. This is so brief that it is perceived as there being no downtime at all.
Figure 6 shows a photograph and list of specifications of the prototype chip utilizing the new technologies described above. Flash memory macros and systems based on these newly developed technologies have been incorporated in the RH850/E2x and RH850/U2x Series MCUs, sample shipments of which have already begun.
Moving forward, Renesas is committed to the continued development of embedded flash memory and striving to achieve the higher capacities, higher speeds, and lower power consumption that will be required to support new applications.
About the author
Yasuhiko Taito has been with Renesas Electronics Corporation working for embedded DRAM and Flash memory development for over 25 years. He is now in charge of the development of cutting edge embedded non-volatile memory for micro controller units.