Measures for maximizing quality
Of course, the main goal of JQ is to bring to volume production a part that will have the lowest possible failure rate in the field. This means that it is important to use automotive-grade parts that are produced and tested to Production Part Approval Process (PPAP) standards. This guarantees that the part itself will have an extremely low failure rate.
Then, to improve quality at the level of the customer’s system, the part must be tested for all known critical issues found in the customer’s usage of earlier parts based on older technology. This approach creates a test protocol that closely simulates the customer’s application. In addition, new features and potentially marginal parameters need to be tested in the customer’s platform to determine whether either the system environment, or the customer’s usage model, are compatible with the new technology’s features and specifications.
To illustrate this point with an example, recent JQs with Cypress customers have tested in the customer’s system new features such as the fast DDR QuadSPI, or the HyperFlash read function, or the latest parallel NOR features on both 65nm and 45nm Flash technology. JQs have also tested the error code correction (ECC) function, which can eliminate potential bit flips.
Experiences and examples
As noted above, it is crucial to plan for system optimisation and failure analysis by preparing the customer platform to connect to a logic analyser. This is not a standard procedure, but it enables the customer and silicon supplier to react immediately when failures occur.
It is particularly difficult to get access to all pins on the PCB when investigating high pin-count parallel NOR Flash memories, or other high pin-count memories in a BGA package.
The Cypress Wingboard is a useful tool for solving this problem (see Figures 1, 2). A small board similar in size to the Flash BGA package, it is soldered between the PCB and the Flash memory module. This board supports matched impedance connectors (MICTORs) for connecting the device to a logic analyser.