Stepping into next generation ADAS multi-camera architectures: Page 4 of 6

December 14, 2016 // By Thorsten Lorenzen, Texas Instruments
Stepping into next generation ADAS multi-camera architectures
Highly integrated approach to achieve extended synchronization and advanced HDR image quality to enable Automotive Surround View & Mirror Replacement Applications.

Central Clock Distribution


A central reference clock applied at the deserializer hub is distributed to all camera modules. In this mode, each serializer is able to derive its clock from the FPD-Link III system link. The serializers drive the clock into the image sensor’s system clock input pin avoiding the camera streams to drift past each other. Operation in this mode offers the advantage that all the cameras can operate in the same clock domain. It eliminates the need for data buffering and re-synchronization.



Figure 3. Central clock distribution supports camera synchronization


Central Frame Synchronized Trigger

Common image sensors offer one frame synchronization input (see FSIN in the block diagram). FSIN controls the image sensor’s capture logic. During normal operation, when the frame synchronization pulse is applied, a new frame will start automatically. Alternatively, one additional line will be introduced to extend the frame height until frame synchronization arrives. An appropriate deserializer hub can generate such a periodic synchronization pulse using its internal timer. The deserializer hub passes the periodic frame sync pulse to all the serializers. In turn, the serializers pass the pulse to each camera using its GPIOs. This concept guarantees frames from all camera streams start simultaneously with a variance of one line maximum.


Figure 4. Frame synchronization controls image sensors


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