New scope for cost and space savings
The problem with existing memory architectures is best illustrated by reference to an application example: a mid-range instrument cluster in a car’s dashboard.
A hybrid (graphical and mechanical) instrument cluster, featuring graphics rendered on a small LCD screen between conventional mechanical dials and gauges, may be implemented with a memory architecture consisting of a microcontroller-based System-on-Chip (SoC), a Synchronous DRAM (SDRAM) scratchpad memory and a high pin-count NOR Flash memory. The fast NOR Flash memory provides fast boot capability, so that static graphics – such as background wallpaper and speed limit warning signs, may be loaded into the SDRAM and from there rendered by the MCU as soon as the driver presses the Start button or turns the key in the ignition. The SDRAM provides scratchpad storage for slow-changing graphics content with a low refresh rate of around 20Hz, such as the fuel gauge and temperature gauge. Highly dynamic content such as maps and navigation instructions, with a refresh rate of typically 60Hz, will be rendered from internal VRAM.
At one time, this architecture would have made use of a legacy parallel Flash interface such as ADP Page Mode. A 512Mbit-density Flash device in a 64-ball BGA package would typically require a high pin count of around 45 for bus communication, providing data throughput of up to 100MB/s. Pressure to reduce pin count led the industry to adopt a serial NOR Flash interface with a much reduced pin count.