Figure 1 reveals the problem with this memory architecture, however: the external SDRAM and external NOR Flash are connected to the microcontroller via separate buses, and might typically require in total as many as 41 pins at the microcontroller for data transactions. There is a large penalty to pay for this in terms of board footprint, complexity and cost.
It was to enable a new memory architecture with a massively reduced pin count that the HyperBus™ interface technology was introduced. Benefiting from the development of special protocol and clocking schemes and dedicated techniques for enhancing data integrity, the HyperBus interface is able to offer higher data throughput rates even than legacy, high-pin count parallel Flash interfaces, but to use a low number of pins, as serial Flash interfaces do. What is more, the RAM and Flash memories can both operate on the same bus at high speed, reducing system pin count further.
The structure of the HyperBus interface is shown in Figure 2. The bus requires only 12 pins: an 8-bit data bus plus control signals, plus a power input and ground. The devices are selected by a Chip Select (CS) signal. The supply voltage is either 1.8V or 3.0V: this is dependent on the host microcontroller. DDR capability is supported at a reduced speed (100MHz) by either a single-ended clock at 3.0V, or a differential clock at full speed (166MHz) at 1.8V.
The implementation of this HyperBus architecture calls for the use of HyperBus-compatible parts. Discrete HyperRAM™ and HyperFlash™ memory ICs are available from Cypress Semiconductor, each housed in a 6mm x 8mm, 24-ball BGA package. The HyperFlash devices are available in 128Mbit, 256Mbit, 512Mbit and 1Gbit densities, and offer up to 333MB/s read bandwidth in DDR mode. The HyperRAM devices, available in 64Mbit and 128Mbit densities, provide up to 333MB/s read/write bandwidth in DDR mode. The temperature grade is -40°C to 125°C for HyperFlash and -40°C to 105°C for HyperRAM.