User interface: A matter of memory: Page 4 of 5

March 15, 2017 //By Marcel Kuba, Cypress Semiconductor
User interface: A matter of memory
How high-speed memory interface technology enables users of DRAM devices to reduce pin count, save space and cut system cost.

Cypress has also introduced the HyperFlash + HyperRAM MCP solution: a system-in-package combining a NOR Flash die and a self-refresh DRAM die in a single 24-ball BGA package. This solution requires 70% fewer pins than the two-chip alternative, reduces board footprint by 77% and offers board design flexibility (see Figure 3).

Cypress also supplies the Amber series of HyperBus-compatible microcontrollers within its Traveo family. Other controllers supporting the HyperBus interface are available from Freescale/NXP, Renesas and Xilinx.

The value of the HyperBus architecture is most clearly expressed by comparisons of data throughput-per-pin. The maximum data throughput from the memory to the MCU via HyperBus is 333MB/s at 1.8V (200MB/s at 3V). The 333MB/s rate is equivalent to 41.6MB/s per pin (333MB/s across eight data pins): a circuit with a similar density but using a Quad SPI Flash interface would offer around half this throughput-per-pin.


Fig. 3: a new SiP reduces the board footprint of the external Flash
and RAM devices by 77% compared to a two-chip solution. 

The increased data throughput-per-pin leads directly to a cost saving compared to other high-speed architectures, as it enables the use of an MCU with fewer pins (smaller, therefore cheaper), and a PCB with fewer layers (cheaper to manufacture and assemble). In many cases, users of HyperBus technology will benefit from both this cost saving and enhanced performance when replacing older SDRAM + NOR Flash systems.

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