The connection between the MCU and HyperFlash and HyperRam in separate packages requires four layers including Vcc and GND (two for the connection). An MCP device, combining the RAM and Flash in a single package, needs one less layer. Interfacing to a Cypress Amber MCU in a Quad Flat Package (QFP), the connections may all be made to pins on one side of the MCU package. When connected to an MCU in a BGA package, more layers would be required (see Figure 4).
The cost and space advantages of the HyperBus architecture, then, are clear when replacing an SDRAM + NOR Flash with a HyperBus-compatible HyperRAM + HyperFlash memory solution. This HyperBus solution is ideal for mid-range graphics applications such as the instrument cluster described above.
Table 1 summarises the memory architecture options today for designers of a broad range of graphics display-based user interfaces: from a low-end system based on SDRAM, up to a high-end system using very high-speed DDR2 DRAM. It shows that HyperRAM offers comparable performance to an SDRAM-133 based system, but with a much lower pin count. DDR2 or DDR3 DRAM offers much higher performance than the HyperRAM system, but is also entails a much higher system cost.
In its HyperBus-compatible product offerings, Cypress has ensured that their BGA package is pin-compatible with all Cypress’s QSPI and dual-QSPI Flash memory devices. For designers wishing to scale up a family of products based on a uniform board layout, therefore, the HyperBus interface offers a simple way to migrate to higher speeds and densities.
And in any circuit, HyperBus technology, and the supporting HyperFlash, HyperRAM and Amber MCU products, offer the best available way to combine high data throughput for advanced graphics rendering with a low pin count and a simple PCB layout which is cheap to produce.
About the author:
Marcel Kuba is Director of Field Applications Engineering, Cypress Semiconductor
Image credits: Cypress Semiconductor