This still, however, leaves the other large component of the system BoM cost of an all-graphics display: the chipset. To satisfy the BoM budget constraints of a mid-range vehicle, a single-chip solution for the entire instrument cluster is required – and this is where migration to the 40nm node has provided a breakthrough. The 40nm node has turned out to be a successful one for the semiconductor industry: yielding well, it is cost-effective while providing great scope to integrate more or better features in a given die size.
And a single-chip instrument cluster design requires a great deal of integration: it might include a high-performance CPU, an LCD controller, high-speed communications interfaces and multiple peripherals. Crucially, it also needs a large, high-speed RAM, since memory capacity is a hard constraint on the display size and display resolution that a system can support.
Lifting memory density while lowering memory requirement
An example of the potential for integration provided by the migration to the 40nm node is provided by the Traveo family of automotive microcontrollers from Cypress Semiconductor. Today’s 40nm Traveo devices offer up to 4MB of embedded Flash memory which operates at up to 80MHz without wait cycles, along with 384kB of SRAM. The new 40nm S6J331X/S6J332X/S6J333X/S6J334X MCUs also integrate an ARM® Cortex®-R5F core, which has an instruction and data cache operating at up to 240MHz and produces 400 DMIPS (see Figure 2).
For many cluster designs, the memory embedded in the S6J33xx devices will be sufficient, helping the designer to minimise costs, power consumption and footprint. If