What the 40nm node means for the instrument cluster: Page 4 of 5

August 02, 2016 //By Mathias Bräuer
What the 40nm node means for the instrument cluster
The 40nm node could enable makers of low- to mid-range vehicles to radically upgrade the traditional instrument cluster. Here's why and how.
rendering of graphics encoded off-chip.

The new Traveo MCUs also integrate an LCD bus controller (see Figure 3). Combined with the display controller, this offers a low-cost means to directly drive displays. The display sub-system’s integral plane has one layer with decompression support. Its fractional plane can combine up to eight layers with different sizes, colour formats and update rates. The eight layers themselves cannot be blended, but both planes can be alpha-blended. All layers can be stored in any memory, including external HyperFlash or HyperRAM memories.


Fig. 3: in the Traveo MCUs, the display controller
and the LCD bus controller share the same 

Reading the available graphics from several sources, this allows a connected display to be driven without the need for a frame buffer, reducing the size of memory required to address any given display size or resolution.

Affordable implementation of advanced graphics in the instrument cluster

Migration to the 40nm node, then, has enabled Cypress to substantially lift the level of integration of functions and capabilities in its Traveo series of automotive MCUs. In particular, the provision of up to 4MB of on-board Flash memory offers the potential for next-generation hybrid clusters’ 2D graphics displays to operate without recourse to external memory, thus dramatically reducing the footprint, power consumption and BoM cost of the system. These next-generation clusters will offer a user experience which has a feel recognisably similar to that of premium vehicles’ full free programmable clusters, but at a fraction of the BoM cost.

The use of a single-chip solution such as a Traveo S6J33xx MCU for these new hybrid instrument clusters also streamlines the development process, since the operation of the entire cluster can be implemented within a single development environment supporting the MCU. What is more, other devices in the Traveo MCU family provide a migration path to higher-end hybrid clusters. The S6J327Cx series, for instance, integrates highly efficient 2D/3D graphics engines, and provides

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