GoldenGate RFIC simulation software raises the bar on performance and usability
This release enhances Agilent’s leadership in advanced-node RFIC design with improved performance, fast mismatch analyses for analog/RF applications and a new easy-to-use graphical user interface. The release also extends the software’s RFIC analysis to more easily incorporate package and board effects.
“There are various ways to approach performance enhancements,” said Paul Colestock, product planning and marketing manager with Agilent’s EEsof EDA organization. “Agilent’s approach is to provide continuous improvement on the circuits that our customers care most about. GoldenGate 2011 stays true to that heritage.”
GoldenGate version 2011 software delivers carrier-analysis improvements that deliver significantly better scalability and performance on multicore CPUs, dramatically improved performance of carrier and SSNA noise analyses, and fast yield-contributor analyses for RF and analog/mixed-signal designers, including DC, AC and oscillator analysis. Enhanced fast circuit-envelope analysis that accelerates RF functional path simulations by an order of magnitude or more, with broader support for RFIC-centric source configurations for models including memory effects. Further, an enhanced crystal oscillator convergence option that reduces the frustration of simulating crystal oscillators.
GoldenGate version 2011 boasts a number of improvements for wireless design verification. Fast mismatch analysis dramatically accelerates the block and functional path verification that RFIC designers perform every day, without loss of accuracy, including new support for Cadence corners tool.
The updated adslib for the GoldenGate library now includes delay-defined transmission lines and Philips-TU Delft standard/user-defined bondwire models. Using this, engineers can simulate more of their designs by including RF package and board effects. Additionally, by closing the loop between system and circuit designers using the new SystemVue and GoldenGate links and flows, designers can greatly accelerate system-level verification of RFICs.
GoldenGate version 2011 also improves both the tool’s usability and in turn, user productivity. A new tree/tabbed graphical user interface for the Cadence Analog Design Environment, for example, eases the configuration of RF analyses and environment/options selection.
For further information: www.agilent.com/find/eesof-goldengate2011.