PLS lines up debug offering for ST’s latest automotive MCUs

PLS lines up debug offering for ST’s latest automotive MCUs

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The UDE test/debug environment is available at the same time as the first MCU samples of STMicroelectronics’ SPC58 E-line multi-core automotive MCUs: PLS says that its UDE version 4.4.6 supports all the MCUs’ functions.
By eeNews Europe

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In partnership with STMicroelectronics, PLS Programmierbare Logik & Systeme (Lauta, Germany) is able to offer the Universal Debug Engine (UDE) 4.4.6 debugging and testing solution, for the first samples of STMicroelectronics new SPC58 E-line in ST’s multi-core automotive microcontroller (MCU) family.

Features of these automotive MCUs include: three Power Architecture based CPU cores (e200z4d), two of which are capable of lockstep, 6320 kB on-chip flash memory, 768 kB SRAM, Generic Timer Module (GTM), Hardware Security Module (HSM), seven Controller Area Network (CAN) nodes, one Time-Triggered Controller Area Network (TTCAN) node, various analogue-to-digital converters and a wide range of additional high-performance peripheral functions. The target applications for these new SPC58 E-line MCUs include engine management, transmission control and advanced driver assistance systems (ADAS).

UDE 4.4.6 allows users to carry out reliable and fast programming of the integrated flash memory as well as the control and management of all active units of the SoC within one consistent user interface. As a result, not only can the main cores be selected as debug target, but also the Generic Timer Module (GTM) and Hardware Security Module (HSM) or the whole device. This high degree of flexibility is supported by a flexible multi-core program loader, which enables loading of program code and data as well as symbol information separately for each individual core.

Management of the individual active units by the debugger is carried out via a special multi-core run control manager, which enables an almost synchronous starting and stopping of the various cores at any time by using logic that is integrated on the chip. Debugging is simplified by the multi-core breakpoints implemented in the UDE. With their help, a simultaneously acting breakpoint for all cores can be set in shared code. Data breakpoints in turn allow the recognition of read and/or write accesses to a variable. Even an expected value can also be optionally taken into account.

The SPC58 E-line SoCs are also available as emulation devices, which are pin-compatible with

production devices. These emulation devices include additional emulation memory, extensive trigger and filter logic as well as connections for a serial high-speed interface based on the Aurora protocol. In order that developers can as simply as possible and abstractly configure the several hundred registers of the additional emulation memory, PLS offers the Universal Emulation Configurator (UEC) with block graphics user interface in addition to the UDE 4.4.6. Measurement tasks can be defined particularly easily with help of the UEC. In doing so, specific states in the target are described by signals. These, in turn, can initiate actions or shift an underlying state machine into a new state.

The Universal Emulation Configurator (UEC) helps the user to cope as effectively as possible with the limited resources of the on-chip emulation memory. In parallel to this, the Aurora interface implementation offers the possibility to externally record a very large amount of trace data, and to carry out a statistical analysis of the program flow such as code coverage and profiling. PLS’ Universal Access Device 3+ (UAD3+) with Aurora pod serves for recording, while the evaluation itself is carried out by the Universal Debug Engine (UDE).

PLS Programmierbare Logik & Systeme; www.pls-mc.com

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