Safety processor family builds bridge to the future of in-car computing
In the field of automation, experts speak of a three-part functional hierarchy: sense, think, act. The new microprocessor from NXP is designed to operate the third part of this chain, “Act”, explained Ray Cornyn, VP and General Manager Vehicle Dynamic Products at NXP. With four lockstep cores working in parallel at a clock cycle of 800MHz, the device offers the by far highest performance of any comparable microprocessor in that application field, Cornyn claims.
The NXP S32S processors use an array of the new Arm Cortex-R52 cores, which integrate the highest level of safety features of any Arm processor (see Fig. 1). The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new “fail availability” capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.
NXP has partnered with OpenSynergy to develop a fully featured, real-time hypervisor supporting the NXP S32S products. OpenSynergy’s COQOS Micro SDK is one of the first hypervisor platforms that takes advantage of the Arm Cortex-R52’s special hardware features. It enables the integration of multiple real-time operating systems onto microcontrollers requiring high levels of safety (up to ISO26262 ASIL D). Multiple vendor independent OS/stacks can also run on a single microcontroller. COQOS Micro SDK provides secure, safe and fast context switching ahead of today’s software-only solutions in traditional microcontrollers.
The S32S line is designed for full support of Autosar 4.0 and other Real-time operating systems. It however is expected to offer some support for the new Adaptive Autosar generation, Cornyn said.
The first of the new S32 product lines, the S32S microprocessors will be sampling in Q4 2018 to so-called alpha customers, NXP said.