SPI NOR flash memory supports transmission speeds up to 400MB/s
As many automotive applications exceed the performance needs of traditional Quad (x4) I/O SPI solutions, Macronix introduced its first x8 I/O SPI solution in the form of the Dual Quad MX66L-85G series and now, taking the performance to the next level, the company is introducing the Octaflash MX25UM family, with SPI backwards compatibility.
OctaFlash is claimed to feature the most comprehensive DTR protocol support in the industry. Input and output cycles of all commands, addresses and information support DTR mode, overcoming the inconvenience of traditional SPI which only supports the STR framework for command input and needs to switch between different protocol modes. Similarly, prior SPIs only supported STR mode when performing program or erase operations and only supported DTR mode when reading, while today’s OctaFlash supports DTR mode for all three operations, saving the time needed to switch between modes.
The current x1 I/O requires 40 clock cycles for complete SPI access including executing commands, addresses and information, while Quad I/O requires 22 clock cycles. In comparison, the next-generation OctaFlash in DTR operation mode needs only 13 clock cycles, significantly reducing the read latency of SPI products and increasing the efficiency of functions such as execute-in-place (XIP).
The device comes in a 24-ball BGA package and operates from either 1.8V or 3V, covering 256MB, 512MB and 1GB densities.
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