Ultra-flat PCB process for high parallel vertical probe card applications

Ultra-flat PCB process for high parallel vertical probe card applications

New Products |
For applications such as DDR3 memory, the requirements for the flatness of boards at wafer level testing become crucial. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Additionally, flatter PCBs require less compliance from the probe interface and reduce interface wear.
By eeNews Europe

Share:

Leveraging the knowledge of PCB stack up engineering and PCB construction, Multitest developed the “UltraFlat” process to meet these requirements. UltraFlat allows for a very tight overall flatness tolerance to be maintained by removing the bow/twist in the PCB. Unlike "flat-baking" that provides a temporarily flat PCB, Mutltitest’s UltraFlat process provides a permanent overall flatness for the PCB. With UltraFlat, Multitest typically is able to comply with bow/twist requirements of 1.0 percent.

More information at www.multitest.com/pcb.

Visit Multitest at www.multitest.com

 

Linked Articles
eeNews Automotive
10s