1838-2019 test standard for 3D chips adds parallel operation
The IEEE has launched a standard to simplify design for test (DfT) for 3D stacks of chips with an option for faster parallel operation.
The IEEE1838-219 standard was initiated by Belgian research group imec and consists of three main elements. DWR, the die wrapper register, defines scan chains at the boundary of each die in the stack to enable modular testing of the internals of each die and of the interconnects between each pair of adjacent dies. SCM, the serial control mechanism, is a single-bit test control mechanism that transports instructions into the stack to control the test modes of the various die wrappers.
The third element, an optional flexible parallel port (FPP), provides a scalable multi-bit test access mechanism to efficiently transport up and down the die stack the large volumes of data typically associated with production test. While DWR and SCM are based on existing DfT standards, while the FPP is new for IEEE Std 1838-2019 and can help to speed up test operations.
“Advances in wafer processing and stack assembly technologies are creating a wealth of different stack architectures,” said Eric Beyne, fellow and program director 3D System Integration at imec. “This causes a sharp increase in the number of potential moments at which testing for manufacturing defects can be executed: pre-bond (before stacking), mid-bond (on partial stacks), post-bond (on complete stacks), and final test (on packaged 3D-ICs).”
“Test equipment contacts ICs via its external interface through probe needles or at test socket,” he explained. “In a die stack, that external interface typically resides in the bottom die of the stack. For the test equipment to be able to deliver test stimuli to and receive responses from the various dies up in the stack, collaboration from the underlying dies is required to provide test access to the die currently being tested.”
An IEEE working group to standardize 3D-DfT was founded in 2011 by Erik Jan Marinissen, scientific director at imec in Leuven, Belgium and he served as its first chair. In recent years, Adam Cron, principal R&D
engineer in the Design Group at Synopsys, has been the driving force as the current chair of the Working Group.
“3D-IC is an important technology to deliver the next wave of innovation as the industry scales past 7nm. Currently, die might come from different suppliers with disjoint DfT architectures. We believe standardizing 3D-DfT will benefit our customers by helping form a consistent stack-level DfT architecture and speeding time to market,” said Amit Sanghani, vice president of engineering in the Design Group at
Synopsys
“A DfT standard like IEEE Std 1838 is important to the industry,” said Wolfgang Meyer, senior group director R&D at Cadence Design Systems. “Die makers know what they must provide, and stack integrators know they can expect. Moreover, EDA suppliers like Cadence can focus their tool support on architectures that are compliant with the new standard. It is good that there is some user-defined scalability with the standard as the 3D-IC field is so wide — a rigid ‘one-size-fits-all’ standard would not work.”
HiSilicon in Shenzhen, China is a potential user of the new IEEE Std 1838. “Per year, we do DfT insertion and automatic test pattern generation (ATPG) for tens of very large and complex digital chip designs in the
most advanced technologies,” said Junlin Huang, manager of a 150-person strong DfT team at the company. “Now, these products start using 3D technology and my DfT team needs to be ready to handle the associated DfT and ATPG challenges. IEEE Std 1838 will help us with that task.”
From February 2020 onward, the new standard IEEE Std 1838-2019 will be available via IEEE Xplore to subscribers of IEEE standards as well as for purchase to everybody else.
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