Fraunhofer IPMS develops TSN IP core family for ADAS use

February 12, 2020 //By Christoph Hammerschmidt
Fraunhofer IPMS develops TSN IP core family for ADAS use
From lane departure warning systems to automatic emergency braking systems: driver assistance systems in modern vehicles are processing more and more data that must be transmitted in real time and sorted according to priority. The Fraunhofer IPMS develops real-time capable IP cores for the automotive sector that meet the Ethernet Time Sensitive Networking (TSN) standard.

An IP design of the Fraunhofer IPMS, the LLEMAC-1G, part of the TSN IP Core product family, meets the highest security level ASIL-D ready according to the ISO standard 26262, which specifies the security requirements for electronic systems to meet special requirements in the automotive sector, so that hardware failures can be prevented or brought under control. The use of the pre-certified IP cores considerably simplifies the approval process for the overall system, since documents relevant to these components, such as the FMEDA (Failure Mode and Effects Analysis) or a safety manual, as well as additional implemented and tested safety features, are already available.

With Fraunhofer IPMS’ TSN IP Core Family, highly safety-relevant electronic systems for the automotive sector can be implemented with real-time-criticality, safety and reliability features. This ensures maximum functional safety for system development in the vehicle. The TSN IP cores can be flexibly implemented in individual ECUs or circuits (system-on-chip, FPGA) using a 32-bit controller interface (8-bit and 16-bit, an AXI4 stream interface, as well as AMBA APB and AHB optional) and fully synchronous description.

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