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Integrity RTOS brings functional safety to RISC V

Integrity RTOS brings functional safety to RISC V

New Products |
By Christoph Hammerschmidt



Integrity and its integrated development environment MULTI solve three key challenges faced by software development teams that will use RISC-V SoCs.

  • Safety and Security – Integrity is based on a separation kernel architecture that provides resource guarantees, hard real-time determinism and was designed to achieve maximum security and safety.
  • Powerful Debugging – The MULTI debugger with its advanced C/C++ compilers and analysis tools is purpose-built to find difficult bugs on complex RISC-V SoCs comprised of multiple heterogeneous cores where the RISC-V core is either the main general-purpose CPU or a secondary special-purpose acceleration core alongside a CPU, such as an Arm core.
  • Production-Ready – Start developing production-ready systems today on leading RISC-V reference boards to meet production requirements for performance, memory efficiency and functional safety (FuSa) through use of Green Hills Integrity and MULTI solutions with their certifications at the highest levels of functional safety for automotive (ISO 26262), industrial systems (IEC 61508) and railway (EN 50128).

This new Integrity support adds to Green Hills’ existing range of products that are optimised for RISC-V and already in use by customers, forming a complete portfolio of mature and production-ready software development solutions for RISC-V. It is integrated with RISC-V processor solutions, including hardware reference boards from Microchip and SiFive, and intellectual property (IP) from SiFive, a leading provider of RISC-V IP. This support enables device manufacturers to reduce the time, cost and complexity of developing and deploying critical software for automotive, military, IoT and industrial solutions based on the new RISC-V processor architecture.

https://www.ghs.com.

 

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