Synopsys rolls ASIL-certified processor IP to ADAS designers

March 08, 2017 //By Christoph Hammerschmidt
Synopsys rolls ASIL-certified processor IP to ADAS designers
Safety-critical functions in ADAS systems and, broadly, in automotive electronics, are required to be designed according to ISO 26262. Synopsys now breaks new ground in this type of applications: The company has developed pre-certified IP that enables SoC designers to integrate proven processor technology into their safety functions, significantly reducing design effort.

Synopsys’ new “ARC EM Safety Island” DesignWare IP contains verified dual-core processors based on Synopsys’s ARC EM4 32-bit processor architecture that support safety criticality in two ways: This IP is already certified to meet ASIL D, the highest level in the risk classification scheme of the ISO 26262 safety standard. Its architecture contains integrated safety monitors as well as a lockstep mechanism, a second “shadow” processor that executes the same code as the main processor to rule out hardware faults. Other features adding safety to the system are multiple hardware safety functions, error correction code (ECC) technology as well as a programmable watchdog timer to detect system failures and runtime errors. This IP will be available initially for Synopsys’ EM4SI and EM5DSI virtual processors; in the second quarter the company plans to add the EM6 and EM7D cores.

ASIL D Ready Certified Dual-Core Lockstep Processors
with Integrated Safety Island

The new IP differs from earlier Synopsys safety packs in that it is supporting ASIL D which requires a lockstep mechanism. Existing safety packs lack this function.

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