Texas Instruments integrates Imagination GPU into Jacinto processor
Texas Instruments (TI) is to use the latest graphics process unit (GPU) core IP from UK developer Imagination Technologies in a range of automotive chip.
TI will use the BXS-4-64 GPU core in its next generation of Jacinto system-on-chip designs. The latest Jacinto 7 family, launched in January and starting to ship now, includes the TDA4VM and DRA829V SoCs for advanced ADAS and automotive gateway systems. These have server performance in a power envelope of 5 to 20W.
Additional SoCs will be introduced throughout the next few years using the BXS core. This provides up to 60 per cent higher performance for automotive graphics applications such as surround view technology. It
The core is the first XS GPU IP with added safety features and a design process conforming to ISO 26262 to help automotive designers achieve ISO 26262 certification. It includes Imagination’s new B-Series multi-core architecture that includes safety mechanisms, such as Tile Region Protection, in addition to existing features such as hardware virtualization.
“Imagination’s BXS GPUs enable us to introduce differentiated automotive processors with higher performance, lower bandwidth and enhanced safety capabilities. IMG’s new multi-core technology also helps us scale our technology for future processor designs,” said Jim Kennedy, Platform Engineering Director for TI Processors.
“TI has been a valued partner of Imagination’s, creating some of the industry-defining SoC for the automotive, industrial and consumer platforms. This license is for a core that is a step beyond anything we’ve delivered before and so we’re excited to see our next generation of GPUs being realised in TI’s next generations of SoCs,” said Jamie Broome, Senior Director Automotive, Imagination Technologies.
The current TDA4VM Jacinto 7 chip uses the 3D GPU PowerVR Rogue 8XE GE8430 running at speeds up to 750 MHz, delivering 96 GFLOPS and processing 6 Gpixel/s. This sits alongside a 1GHz C7x floating point vector DSP, two C66x floating point DSPs and an 8TOPS deep-learning matrix multiply accelerator (MMA). There are also Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators alongside Depth and Motion Processing Accelerators (DMPAC), dual 64bit ARM Cortex-A72 microprocessor cores and six ARM Cortex-R5F real time MCUs, two in an isolated MCU subsystem and four in a general compute partition.
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