Cadence Design Systems has developed platform that accelerates the creation of virtual and hybrid prototypes of complex systems across hardware and software.
The Helium Studio enables early software bring-up for hardware-software co-verification and co-debug, provides comprehensive support for platform assembly, enables the creation and debug of virtual models and offers a rich library of pre-built virtual models and hybrid adapters. Using the system, verification with a virtual or hybrid model of the SoC is not just orders of magnitude faster than verification with a pure RTL model, it enables early software bring-up before the RTL is available let alone the silicon of a complex chip.
The tool is designed with native interfaces to the Cadence verification engines, including the Palladium Z2 Enterprise Emulation Platform, the Protium X2 Enterprise Prototyping Platform and Xcelium Logic Simulator to provide software developers with a uniform debug experience from virtual model to RTL.
The tool has already been used for the design of graphics and 5G chips.
“The ability to boot a commercially available OS and run industry benchmarks for our latest GPUs and SoCs before silicon is available is critical for our first-pass success and time-to-market goals,” said Narendra Konda, senior director of Hardware Engineering at GPU designer Nvidia.
“Using the Cadence Helium Virtual and Hybrid Studio, which is natively integrated with the Palladium and Protium platforms, we are able to find and fix many software and RTL bugs pre-silicon. The order of magnitude throughput improvement we achieved with the hybrid platform allowed us to perform long-running tests in a pre-silicon environment. The Helium Studio’s unique gearshift technology lets us hot-swap software execution from virtual to RTL dynamically, giving us the software bring-up speed and the accuracy of RTL when needed. The Helium Studio’s embedded software debug capability enables uniform hardware-software co-debug whether running on software on a virtual core or RTL